Partial Scan and Full Scan Implementations Partial scan and full scan are two widely used techniques for testing and verifying the testability of VLSI circui...
Partial scan and full scan are two widely used techniques for testing and verifying the testability of VLSI circuits. These methods offer different levels of detail and flexibility, leading to different trade-offs between time and cost.
Partial scan:
Starts by testing individual blocks or small portions of the circuit.
Provides detailed information about the functional behavior of the block.
Less time-consuming than full scan.
Less accurate than full scan.
Full scan:
Tests the entire circuit by traversing all the connections and nodes.
Provides a complete picture of the circuit's behavior.
More time-consuming than partial scan.
More accurate than partial scan.
Benefits of partial scan:
Useful for quickly identifying design issues.
Can be used to verify simple designs or verify specific functionality.
Benefits of full scan:
Provides more accurate functional verification.
Useful for complex designs with many interconnections.
Trade-offs:
Partial scan is faster but provides less detail.
Full scan is more accurate but takes longer.
Examples:
Partial scan: Testing individual SRAM blocks in a chip.
Full scan: Testing the entire memory controller chip, including connections to other components.
Applications:
Partial scan is often used for initial verification and during design cycle testing.
Full scan is typically used for final testing and verification after the circuit is fully integrated