Boundary Scan Standard (IEEE 1149.1) The Boundary Scan standard (IEEE 1149.1) is a formal specification for testability in VLSI (Very Large Scale Int...
The Boundary Scan standard (IEEE 1149.1) is a formal specification for testability in VLSI (Very Large Scale Integration) design. It helps designers create testable chips by defining design features and their interactions with the surrounding environment.
Key concepts covered in the standard:
Boundary scan: A technique for accessing the interior of a chip without physically disassembling it.
Boundary scan interface: A set of test signals and ports used to control and read boundary scan features.
Testability criteria: Specifications for how well the chip can be tested with boundary scan.
Testability features: Design elements like memory cells, registers, and control signals that can be tested using boundary scan.
Testability modes: Different techniques for accessing boundary scan features, such as scan chains and scan chains with repeaters.
Benefits of implementing boundary scan standard:
Improved testability: Boundary scan allows designers to test more complex chip features without physically disassembling the chip.
Reduced development costs: By identifying testability features early in the design phase, designers can avoid expensive redesign efforts later.
Enhanced design flexibility: Designers can incorporate additional features and test cases by using boundary scan.
Examples:
A boundary scan interface can include signals like CS (Chip Select), OE (Output Enable), and ADDR (Address Register).
A memory cell can be tested by asserting values on specific boundary scan signals and measuring the output.
A scan chain with repeaters can be used to access all memory cells in a chip.
Note: This is a complex topic and a thorough understanding of the standard is recommended for VLSI designers