Leakage Power Mechanisms in CMOS Leakage power is a significant contributor to power dissipation in CMOS chips. It refers to the flow of charge carriers (ele...
Leakage power is a significant contributor to power dissipation in CMOS chips. It refers to the flow of charge carriers (electrons and holes) through the material within the CMOS device that is not intended for active device operation.
There are two main types of leakage power mechanisms in CMOS:
1. Subthreshold leakage:
This mechanism involves the leakage of charge carriers across the depletion region (the region between the source and drain contacts).
Due to the smaller size and lower voltage of the depletion region, subthreshold leakage is typically much lower than gate oxide leakage.
2. Gate oxide leakage:
This mechanism involves the leakage of charge carriers across the insulating oxide layer that separates the gate and source/drain contacts.
Gate oxide leakage is significantly higher than subthreshold leakage because of the larger size and higher voltage of the gate oxide.
Leakage power can be minimized by optimizing the CMOS device design and choosing materials with low leakage current density. This allows for efficient power delivery to the active device while minimizing power dissipation