Glitching Power and Logical Effort Glitching power and logical effort are two critical yet distinct aspects of low power VLSI design that significantly impac...
Glitching power and logical effort are two critical yet distinct aspects of low power VLSI design that significantly impact the overall power consumption of a circuit. While they are often used interchangeably, understanding their differences is essential for achieving efficient circuit design.
Glitching Power:
Glitching power refers to the energy that a CMOS circuit spends in the inactive, "off" state.
It primarily occurs when a gate is left floating, leading to a random charge distribution.
This charge leakage can significantly degrade the performance of the circuit, even when the gate is driven.
Logical Effort:
Logical effort refers to the energy required to activate a gate, regardless of the input signal.
It encompasses the gate't resistance, gate leakage current, and the time it takes for the gate to reach a stable voltage.
Lowering the logical effort helps to reduce power consumption, as it reduces the time the gate remains in the "on" state.
The Trade-off between Glitching Power and Logical Effort:
Both glitching and logical effort contribute to the overall power consumption of a CMOS circuit.
Balancing these two factors requires careful consideration during circuit design.
Designers often employ techniques like supply voltage regulation, buffering, and signal integrity optimization to achieve the desired balance.
Examples:
One approach to reducing glitching power is to use a weak gate driver that requires more time to reach a stable state. This can effectively prevent the charge leakage that contributes to glitching.
Another technique is to optimize the supply voltage and gate drive currents to minimize the impact of variations in power supply noise.
Implementing appropriate logic optimization techniques, such as data skew reduction, can also help to improve the overall efficiency of the circuit