Chapter 1

Power Dissipation in CMOS

Sources of power dissipation (Dynamic, Static, Short-circuit)

medium • 1 min read

Dynamic power equations and switching activity

medium • 2 min read

Leakage power mechanisms (Subthreshold, Gate oxide)

medium • 3 min read

Glitching power and logical effort

medium • 4 min read

Metrics for power, delay, and area trade-off

medium • 5 min read

Chapter 2

Circuit-Level Power Minimization

Transistor sizing for energy efficiency

medium • 1 min read

Multi-VDD and Multi-Vth assignment techniques

medium • 2 min read

Dynamic Voltage and Frequency Scaling (DVFS)

medium • 3 min read

Adaptive Body Biasing (ABB)

medium • 4 min read

Adiabatic logic principles

medium • 5 min read

Chapter 3

Architecture-Level and Logic-Level Techniques

Clock gating strategies and implementation

medium • 1 min read

Power gating and sleep transistor sizing

medium • 2 min read

State encoding for low switching activity

medium • 3 min read

Pre-computation logic approaches

medium • 4 min read

Pipelining and parallelism for power reduction

medium • 5 min read

Chapter 4

Memory and Interconnect Power

Low power SRAM architectures

medium • 1 min read

Sense amplifier optimizations

medium • 2 min read

Interconnect capacitance scaling

medium • 3 min read

Bus encoding techniques (Bus-invert coding)

medium • 4 min read

Low swing signaling

medium • 5 min read

Chapter 5

Power Estimation and Analysis

RTL and gate-level power simulation methodologies

medium • 1 min read

Probabilistic power analysis techniques

medium • 2 min read

UPF/CPF formats for power intent specification

medium • 3 min read

Thermal considerations in IC design

medium • 4 min read

Reliability issues related to high power density

medium • 5 min read