Path delay and transition delay fault models Path delay models predict the time it takes for a signal to travel from a source to a destination on a chip....
Path delay models predict the time it takes for a signal to travel from a source to a destination on a chip. These models are used to analyze the impact of delays in the chip's path on the overall system performance.
Transition delay models predict the time it takes for a signal to change state on a chip. These models are used to analyze the impact of delays in the chip's transition on the overall system performance.
Common fault models that can be represented using path delay and transition delay models include:
Single stuck-at fault (SFSF): An SFSF is a fault where a single gate is stuck in a "high" or "low" state.
Stuck-at-set/reset fault (SASR): An SASR is a fault where a gate is stuck in a "set" or "reset" state.
Read-only memory (ROM) read fault: A ROM read fault is a fault that occurs when the chip is trying to read data from an ROM location, but the data is not available.
Stuck-at-logic-level fault (STFL): A STFL is a fault where a gate is stuck at a specific logic level, such as "1" or "0".
Path delay and transition delay models are important because they can be used to:
Identify potential fault locations in a chip.
Prioritize testing efforts for fault mitigation.
Analyze the impact of different design changes on system performance.
Here's an example of how a path delay model can be used to analyze a fault:
Consider a path with two gates, A and B. If the path delay model shows a delay of 10 nanoseconds between gates A and B, this means that it will take 10 nanoseconds for the signal to travel from A to B. If a stuck-at-set fault occurs in either gate A or gate B, it will cause a delay of 10 nanoseconds. Therefore, this fault will have a significant impact on the system performance