Netlist Formats and DEF/LEF Library Syntax Netlist formats and the DEF/LEF library syntax are essential for describing the physical layout of electronic circ...
Netlist formats and the DEF/LEF library syntax are essential for describing the physical layout of electronic circuits. These formats define the connections and attributes of various components, including transistors, resistors, capacitors, and other passive and active devices.
Netlist formats are typically text-based files that describe the circuit in a hierarchical manner. The primary format is the SystemVerilog Netlist format (SVF), which is widely supported by various tools and verification software.
Within the SFF format, components are defined using symbols. Each symbol represents a specific physical device with its own set of attributes, such as name, net name, type, location, and connections. The SFF format is highly flexible and allows for complex circuit representation.
The DEF/LEF (Device, Fabrication, and Layout Exchange Format) library syntax is a more specialized format designed for use within formal verification and layout tools. It is essentially a meta-language that can be used to define device structures and their relationships within the netlist.
The DEF/LEF format employs a different approach to netlist description. Instead of directly defining individual components, it uses net names and net connections to represent the circuit structure. This approach simplifies the netlist and allows tools to automatically generate netlist instances based on the defined net connections.
Here's a simple example of a netlist using both formats:
SFF format:
// Bipolar transistor
Vcc Vdd 0 100u;
M1 N1 N2 0 100u;
// Capacitor
C1 N3 N4 0 100u;
// Resistor
R1 N1 N3 0 10k;
DEF/LEF format:
// Device definition for transistor
.model transistor NMOS (
L 100u W 50u
Vto 0.7
Vdd 0.7
);
// Device definition for capacitor
.model capacitor
(
C 100u 0
Vin 100u 0
Vout 0 100u
);
// Device definition for resistor
.model resistor
(
R 10k 0
Rname N1 N2
);
Both formats achieve the same goal of representing the circuit. However, the DEF/LEF format offers greater abstraction and automation, while the SFF format provides greater flexibility and control for specific verification and layout tools