Chapter 1
Introduction to Physical Design
VLSI physical design cycle (Floorplanning to Sign-off)
medium • 1 min read
Netlist formats and DEF/LEF library syntax
medium • 2 min read
Delay models (Elmore, NLDM, CCS, ECB)
medium • 3 min read
RC extraction and interconnect modeling
medium • 4 min read
Complexity analysis of CAD algorithms
medium • 5 min read
Chapter 2
Partitioning and Floorplanning
Graph partitioning models and algorithms
medium • 1 min read
Kernighan-Lin and Fiduccia-Mattheyses heuristics
medium • 2 min read
Floorplanning representations (Slicing trees, Polish expressions)
medium • 3 min read
Simulated annealing for floorplan optimization
medium • 4 min read
Pin assignment and I/O pad placement
medium • 5 min read
Chapter 3
Placement Methods
Global placement vs detailed placement
medium • 1 min read
Wirelength estimation (HPWL) and objectives
medium • 2 min read
Force-directed placement algorithms
medium • 3 min read
Analytical placement (Quadratic, Non-linear optimization)
medium • 4 min read
Legalization strategies for standard cells
medium • 5 min read
Chapter 4
Routing Algorithms
Chapter 5
Clock and Power Network Design
Clock Tree Synthesis (CTS) algorithms (H-Tree, MMM)
medium • 1 min read
Clock routing for zero skew and bounded skew
medium • 2 min read
Power ground (P/G) grid structures
medium • 3 min read
IR drop and Electromigration (EM) analysis methodologies
medium • 4 min read
Physical verification (DRC, LVS, ERC)
medium • 5 min read