1T-1C DRAM Cell Structure and Operation 1T-1C Cell A 1T-1C DRAM cell consists of a single transistor, a capacitor, and a memory cell. It is the basic bu...
1T-1C DRAM Cell Structure and Operation
1T-1C Cell
A 1T-1C DRAM cell consists of a single transistor, a capacitor, and a memory cell. It is the basic building block of dynamic random-access memory (DRAM).
Capacitor
The capacitor holds the charge required to set the memory cell to its desired state. The size of the capacitor is typically determined by the chip size and power supply voltage.
Memory Cell
The memory cell is a semiconductor device that can store a single bit of information. In a DRAM cell, the memory cell is an n-channel transistor that is heavily doped with impurities of opposite charge.
Operation
When the input gate of the transistor is biased positively, it acts as a p-channel device and allows current to flow from the source to the drain.
This current charges the capacitor connected to the drain of the transistor.
When the input gate is biased negatively, it turns the transistor into an n-channel device, blocking current flow from the source to the drain.
This prevents the capacitor from being charged, effectively setting the memory cell to its "off" state.
By varying the voltage of the input gate, the charge on the capacitor can be changed, allowing the memory cell to store a single bit of information.
Example
A 1T-1C DRAM cell with a 100nF capacitor and a 1V supply voltage can be implemented with the following circuit:
Source - Gate - Drain
| + |
|Capacitor |
| - |
Gate - Drain - Charge Pump
Conclusion
The 1T-1C DRAM cell is a fundamental building block of DRAM technology. It allows for the storage and retrieval of single bits of information using a single transistor, capacitor, and memory cell