Interface Synthesis and Wrapper Creation Interface synthesis is a crucial step in SoC design where multiple functional blocks are combined to create a co...
Interface synthesis is a crucial step in SoC design where multiple functional blocks are combined to create a complete interface. This involves mapping the interface requirements onto the available interface resources and then connecting the blocks to implement the necessary functionality.
Wrapper creation involves generating platform-specific code that can be used by synthesis tools to generate the necessary interface files. This allows different synthesis tools to be used with the same design, regardless of the target platform.
Benefits of synthesis and wrapper creation:
Reduced design time and effort: By automatically generating interface files, synthesis tools can significantly reduce the design time and effort required.
Increased flexibility: Wrapper creation allows designers to choose the right tools for the job based on the target platform, reducing the need to manually generate interface files for each tool.
Improved maintainability: By separating the design concerns from the synthesis process, wrapper creation facilitates easier maintenance and modification of the design.
Here's an example to illustrate the difference between synthesis and wrapper creation:
Synthesis:
The design team defines the interface specifications (e.g., bus width, signal names, data types).
Synthesis tools then automatically generate the interface files (e.g., bus description files) for the target platforms (e.g., FPGA, ASIC).
Wrapper creation:
The design team provides the synthesis tools with the interface specifications.
The wrapper generator uses these specifications to generate platform-specific code, including bus drivers and signal routing files.
Examples:
In the context of FPGA design, interface synthesis would create bus and memory interface files for the FPGA, while wrapper creation would generate platform-specific code for interfacing with the FPGA.
Similarly, in the context of ASIC design, interface synthesis would generate high-level interface specifications, while wrapper creation would generate platform-specific code for interfacing with the ASIC