Chapter 1

Introduction to Logic Synthesis

RTL-to-Gates synthesis flow

medium • 1 min read

Translation, optimization, and technology mapping

medium • 2 min read

Boolean algebra and two-level logic optimization

medium • 3 min read

Quine-McCluskey method and Espresso algorithm

medium • 4 min read

Multi-level logic optimization networks

medium • 5 min read

Chapter 2

State Machine and Sequential Synthesis

State encoding assignments (One-hot, Binary, Gray)

medium • 1 min read

FSM optimization and state reduction

medium • 2 min read

Retiming in sequential circuits

medium • 3 min read

Clock skew scheduling and synchronization

medium • 4 min read

Synthesis of synchronous and asynchronous circuits

medium • 5 min read

Chapter 3

Formal Verification Fundamentals

Simulation versus Formal Verification

medium • 1 min read

Equivalence checking (Combinational and Sequential)

medium • 2 min read

Binary Decision Diagrams (BDDs) applications

medium • 3 min read

Satisfiability (SAT) solvers for verification

medium • 4 min read

Model checking basics and Temporal Logic (CTL, LTL)

medium • 5 min read

Chapter 4

Functional Verification Methodologies

Coverage-driven verification

medium • 1 min read

Code coverage and functional coverage metrics

medium • 2 min read

Constrained random stimulus generation

medium • 3 min read

Assertion-Based Verification (SVA)

medium • 4 min read

Universal Verification Methodology (UVM) concepts

medium • 5 min read

Chapter 5

Timing Verification

Static Timing Analysis (STA) algorithms

medium • 1 min read

False paths and multicycle paths

medium • 2 min read

On-chip variation (OCV) modeling

medium • 3 min read

Statistical Static Timing Analysis (SSTA)

medium • 4 min read

Timing sign-off corners

medium • 5 min read