Chapter 1
Digital System Design Fundamentals
Review of combinational and sequential logic
medium • 1 min read
Timing analysis and critical path computation
medium • 2 min read
Synchronous and asynchronous finite state machines
medium • 3 min read
Mealy and Moore machines design
medium • 4 min read
Metastability and synchronization techniques
medium • 5 min read
Chapter 2
Hardware Description Languages
Verilog HDL basics and data types
medium • 1 min read
Behavioral, dataflow, and structural modeling
medium • 2 min read
SystemVerilog for design and verification
medium • 3 min read
Testbench creation and simulation strategies
medium • 4 min read
Synthesizable vs. non-synthesizable constructs
medium • 5 min read
Chapter 3
Advanced FPGA Architecture
Architecture of typical FPGAs (Xilinx, Altera)
medium • 1 min read
Configurable Logic Blocks (CLBs) and interconnects
medium • 2 min read
Embedded blocks: DSP slices, Block RAMs
medium • 3 min read
FPGA design flow (synthesis, map, place, route)
medium • 4 min read
Partial reconfiguration techniques
medium • 5 min read
Chapter 4
Datapath and Control Design
Design of high-speed adders (Carry lookahead, Carry skip)
medium • 1 min read
Multiplier architectures (Booth, Wallace tree)
medium • 2 min read
ALU design methodologies
medium • 3 min read
Control unit design (hardwired and microprogrammed)
medium • 4 min read
Pipelined datapath design and hazards
medium • 5 min read
Chapter 5
Clocking and Timing Issues
Clock distribution networks and skew management
medium • 1 min read
Gated clocks and clock domain crossing (CDC)
medium • 2 min read
Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs)
medium • 3 min read
Static Timing Analysis (STA) principles
medium • 4 min read
Setup and hold time violation fixes
medium • 5 min read