Chapter 1

Machine Instructions

Addressing modes

medium • 1 min read

Instruction formats

medium • 2 min read

Opcode design

medium • 3 min read

Zero-address instructions

medium • 4 min read

Data transfer

medium • 5 min read

Chapter 2

ALU and Data-path

Control unit

medium • 1 min read

Hardwired control

medium • 2 min read

Micro-programmed control

medium • 3 min read

Data-path design

medium • 4 min read

Register transfer

medium • 5 min read

Chapter 3

Instruction Pipelining

Pipeline stages

medium • 1 min read

Throughput and speedup

medium • 2 min read

Pipeline hazards

medium • 3 min read

Data dependency

medium • 4 min read

Control hazards

medium • 5 min read

Chapter 4

Memory Hierarchy

Cache memory

medium • 1 min read

Main memory

medium • 2 min read

Secondary storage

medium • 3 min read

Virtual memory

medium • 4 min read

TLB

medium • 5 min read

Chapter 5

I/O Interface

Interrupts

medium • 1 min read

Direct Memory Access (DMA)

medium • 2 min read

Isolated vs Memory-mapped I/O

medium • 3 min read

Polling

medium • 4 min read

Peripheral control

medium • 5 min read

Chapter 6

Cache Design

Direct mapping

medium • 1 min read

Set associative mapping

medium • 2 min read

Replacement policies

medium • 3 min read

Write-through policy

medium • 4 min read

Write-back policy

medium • 5 min read

Chapter 7

Processor Design

CISC vs RISC

medium • 1 min read

Fetch-decode-execute

medium • 2 min read

Superscalar

medium • 3 min read

VLIW

medium • 4 min read

Vector processors

medium • 5 min read

Chapter 8

System Bus

Bus arbitration

medium • 1 min read

Bus timing

medium • 2 min read

PCI

medium • 3 min read

SCSI

medium • 4 min read

Serial bus

medium • 5 min read